The present invention is related in general to the field of electronic systems and semiconductor devices and more specifically to a structure and method of low voltage silicon controlled rectifier for preventing destructive electrostatic discharge in high voltage failsafe applications.
Integrated circuits (ICs) may be severely damaged by electrostatic discharge (ESD) events. A major source of ESD exposure to ICs is from the charged human body (xe2x80x9cHuman Body Modelxe2x80x9d, HBM); the discharge of the human body generates peak currents of several amperes to the IC for about 100 ns. A second source of ESD is from metallic objects (xe2x80x9cmachine modelxe2x80x9d, MM); it can generate transients with significantly higher rise times than the HBM ESD source. A third source is described by the xe2x80x9ccharged device modelxe2x80x9d (CDM), in which the IC itself becomes charged and discharges to ground in the opposite direction than the HBM and MM ESD sources. More detail on ESD phenomena and approaches for protection in ICs can be found in A. Amerasekera and C. Duvvury, xe2x80x9cESD in Silicon Integrated Circuitsxe2x80x9d (John Wiley and Sons LTD. London 1995), and C. Duvvury, xe2x80x9cESD: Design for IC Chip Quality and Reliabilityxe2x80x9d (Int. Symp. Quality in El. Designs, 2000, pp. 251-259; references of recent literature).
ESD phenomena in ICs are growing in importance as the demand for higher operating speed, smaller operating voltages, higher packing density and reduced cost drives a reduction of all device dimensions. This generally implies thinner dielectric layers, higher doping levels with more abrupt doping transitions, and higher electric fieldsxe2x80x94all factors that contribute to an increased sensitivity to damaging ESD events.
The most common protection schemes used in metal-oxide-semiconductor (MOS) ICs rely on the parasitic bipolar transistor associated with an nMOS device whose drain is connected to the pin to be protected and whose source is tied to ground. The protection Level or failure threshold can be set by varying the nMOS device width from the drain to the source under the gate oxide of the nMOS device. Under stress conditions, the dominant current conduction path between the protected pin and ground involves the parasitic bipolar transistor of that nMOS device. This parasitic bipolar transistor operates in the snapback region under pin positive with respect to ground stress events.
The dominant failure mechanism, found in the nMOS protection device operating as a parasitic bipolar transistor in snapback conditions, is the onset of second breakdown. Second breakdown is a phenomenon that induces thermal runaway in the device wherever the reduction of the impact ionization current is offset by the thermal generation of carriers. Second breakdown is initiated in a device under stress as a result of self-heating. The peak nMOS device temperature, at which second breakdown is initiated, is known to increase with the stress current level.
In U.S. Pat. No. 4,939,616, issued on Jul. 3, 1990 (Rountree, xe2x80x9cCircuit Structure with Enhanced Electrostatic Discharge Protectionxe2x80x9d), a silicon controlled rectifier (SCR) is described as a protection device against ESD wherein the trigger mechanism is avalanche conduction at the interface between the n-well surrounding a portion of the protection device and the p-type substrate. The lowered threshold voltage is provided by a highly doped region of the same conductivity type as the well at the interface between the well and the substrate. This highly doped region is connected to a resistor which is then connected to the protected node. The resistor and heavily doped region at the intersection between the n-well and substrate provide an additional source of current for avalanching at a lower voltage. Thus the trigger voltage of the protection system is substantially lowered. For today""s miniaturized circuit elements, however, the SCRs of the quoted patent are not fast enough and the described protection, therefore, not efficient enough.
In U.S. Pat. No. 5,903,032, issued on May 11, 1999 (Duvvury, xe2x80x9cPower Device Integration for Built-in ESD Robustnessxe2x80x9d), covers the basic concept of a drain-extended (DE) nMOS transistor integrated with an SCR. However, the patent does not describe the technique for silicided technologies with lightly doped drain junctionsxe2x80x94a structure and process commonly employed today. The patent is not sufficient for today""s advanced CMOS technologies, which include shallow trench isolation, low resistance substrates, and silicided diffusions, all of which would essentially degrade the bipolar gains of the pnp and the npn transistors.
An urgent need has, therefore, arisen for a coherent, low-cost method of enhancing ESD insensitivity without the need for additional, real-estate consuming protection devices. The device structures should further provide excellent electrical performance, mechanical stability and high reliability. The fabrication method should be simple, yet flexible enough for different semiconductor product families and a wide spectrum of design and process variations. Preferably, these innovations should be accomplished without extending production cycle time, and using the installed equipment, so that no investment in new manufacturing machines is needed.
A semiconductor circuit for multi-voltage operation having built-in electrostatic discharge (ESD) protection is described, comprising a drain extended nMOS transistor and a pnpn silicon controlled rectifier (SCR) merged with the transistor so that a dual npn structure is created and both the source of the transistor and the cathode of the SCR are connected to electrical ground potential, forming a dual cathode, whereby the ESD protection is enhanced. The rectifier has a diffusion region, forming an abrupt junction, resistively coupled to the drain, whereby the electrical breakdown-to-substrate of the SCR can be triggered prior to the breakdown of the nMOS transistor drain. The SCR has anode and cathode regions spaced apart by semiconductor surface regions and insulating layers positioned over the surface regions with a thickness suitable for high voltage operation and ESD protection.
For improved ESD protection, the invention uses a transistor with high breakdown voltage and complements it with a low voltage SCR that has a low and fast trigger voltage. The low and fast trigger voltage is accomplished by creating high gain npn and pnp parasitic transistors using a fabrication method characterized by two features:
blocking the lightly doped drain implant over the area of the STI-blocked SCR. The invention provides a selective process by opening a window in a photoresist layer so that a low energy, low dose ion implant creates shallow, lightly doped layers under the surface only in regions for the extended source and drain of the MOS transistor;
and
selecting localized silicon nitride walls in a thickness sufficient to block the medium energy ion implant required for creating the deep source and drain regions.
In another embodiment of the invention, the process steps are reversed: The source drain implant is performed first and the silicon nitride walls are applied subsequently.
The device structure of the invention can be manufactured by two distinctly different process flows:
Self-aligned STI-blocked SCR: The silicide blocking process step, actualized by patterned silicon nitride layers over the bases of the pnp and npn portions of the SCR, occurs before the source/drain implants. In this process, the silicon nitride is thick enough to prevent source/drain implant as well as silicide formation.
Non-aligned STI-blocked SCR: First, the SCR bases are defined by the n+ and p+ source/drain (S/D) implants. Second, a layer of silicon nitride or silicon dioxide is patterned to protect the SCR except for fractional surface portions of the SCR anode and cathode. Third, these unprotected portions are silicided.
In both process variations, silicide formation is prevented over the bases of the bipolar elements (pnp and npn transistors). Consequently, electrical shorts between the bases and their corresponding emitters/collectors are prevented.
It is an aspect of the invention to merge an SCR and a MOS transistor by forming only a single well of a conductivity type opposite to the conductivity type of the tank in which the well is embedded. In the example of a p-tank, the well is an n-well and the SCR is pnpn.
Another aspect of the invention is to increase ESD protection by a dual npn structure in the SCR, firstly p-diffusion/n-well/p-tank, and secondly p-diffusion/n-diffusion/p-tank. This dual structure is enabled by the aspect of the invention to use a thick silicon nitride layer as protection of the semiconductor surface regions (base of SCR) from medium-energy n-type ion implantation, thus allowing efficient current flow from p-diffusion to n-diffusion through lightly doped semiconductor material.
Another aspect of the invention is to leave this thick silicon nitride on the SCR for suppressing the silicide formation at the junctions, which would not allow the SCR to trigger before reaching the failure point of the built-in nMOS npn. Taking advantage of the lower breakdown voltage of the junctions initiates the SCR trigger before the avalanche of the high voltage transistor.
Another aspect of the invention is to provide ESD protection for high voltage failsafe applications without bias current and sufficiently low and fast trigger voltage (failsafe I/O circuits are circuits on the bond pad that have no path for dc current regardless whether the device is powered xe2x80x9conxe2x80x9d or xe2x80x9coffxe2x80x9d).
Another aspect of the invention is to require fewer ESD resistors for ESD protection than conventional protection circuits. This is an advantage because ESD resistors increase driver size and output capacitance.
Another aspect of the invention is to provide protection compatible with the high voltage transistor junction by integrating the SCR into the device structure of the high voltage transistor structure and designing for a lower breakdown of the SCR.
Another aspect of the invention is to maximize the ESD protection by reducing the shallow trench isolation width spacing the drain of the MOS transistor and the anode of the SCR to zero.
The invention applies to semiconductors both of p-type and n-type as xe2x80x9cfirstxe2x80x9d conductivity types. The invention is equally applicable to nMOS and pMOS transistors; the conductivity types of the semiconductor and the ion implant types are simply reversed.
The technical advances represented by the invention, as well as the aspects thereof, will become apparent from the following description of the preferred embodiments of the invention, when considered in conjunction with the accompanying drawings and the novel features set forth in the appended claims.